The present invention relates to a simplified process for the definition of a tunnel area in non-volatile semi-conductive non-self-aligning memory cells.
The invention relates in particular, but not exclusively, to the production of EEPROM FLOTOX memory cells and the following description is made with reference to this field of application with the sole objective of simplifying its explanation.
It is well known that EEPROM type memory cells are formed by a field effect transistor equipped with a floating gate capacitively coupled to a control gate terminal. Such a floating gate transistor is connected in series to a selection transistor.
The floating gate is formed by a first layer of polysilicon, so-called polyl; while the control gate is formed by an overlaying second layer of polysilicon, so called poly2.
While in the memory cells the layers of poly1 and poly2 are separated by an intermediate interpoly dielectric layer, the selection transistor gate is formed by only one layer of poly.
FIGS. 1 and 1a show from above and in cross-section, respectively a portion of a semi-conductive sublayer 10 including a single conventional EEPROM memory cell 1 including a field effect transistor 2 equipped with a floating gate 3 capacitively coupled to a control gate terminal 4. The floating gate transistor 2 is connected in series to a selection transistor 5.
The floating gate 3, in which the charges are stored, is formed by the first layer of poly1, while the gate control 4 is formed by the second layer of poly2.
A thin layer of tunnel oxide 6, having a thickness of about 80 Angstroms, is provided between the floating gate 3 and the semi-conductive sublayer 10. Electrical charges pass via this tunnel oxide 6 due to the Fowler-Nordheim effect, during the memory cell 1 programming phase.
A diffused area formed in the sublayer 10 and partially below the region of the gate, is destined for a capacitor implant which helps to form a pocket of electrons which allows for an efficient injection by the Fowler-Nordheim tunnel effect.
In the newest generation technology, the tunnel area 6 is defined by means of a stripe which is situated in part under the floating gate 3, and which represents the actual tunnel area 6, and partly on the outside in the direction of the selection transistor 5. The portion extending outside the floating gate is indicated with 7 in FIG. 1a. This arrangement reduces the lithographic and tunnel area etching criticalness, as shown in FIGS. 1 and 1a. written paragraph:
This known solution presents a problem because an edge or step 11 is created in the layer of thick oxide 12 between the selection transistor 5 and the floating gate 3. This step 11 notably complicates the removal of the thick layer of oxide 12 necessary for following phases of the non-Double Short Circuited Polysilicon (DSCP) non-self-aligned process for the production of EEPROM memories. Typically after the definition of the floating gate, that is of the layer of polyl, the thick oxide 12 is etched to then make the gate oxides of the circuitry associated with the cell matrix. This etching of thick oxide 12 must reach the surface of the semi-conductor 10 without damaging it.
Nevertheless, in the presence of disuniformities of the oxide itself, such as those due to the step 11, the etching phase can be problematic because there is the risk of overetching the thick oxide 12 in some areas in order to be able to remove it completely in others.
An embodiment of the present invention includes a non-DSCP and non-selfaligned process flow of a simplified type having characteristics such as to permit the production of semi-conductive FLOTOX EEPROM type memory cells having a uniform layer of oxide on all the active areas even after the growth of the tunnel oxide.
In embodiments of the invention, the tunnel mask is designed in such a way as to remove all the thick oxide except that in the sensing transistor area, that is to say in the portion of memory cell comprised between the capacitor plant and the source diffusion. This allows for a uniform oxide on all of the active areas which can be removed in an easier way than in the prior art.
A simplified non-DSCP process for defining the tunnel area in non-volatile memory cells with semi-conductive floating gate which are non-aligned and incorporated in a cell matrix with associated control circuitry, to each cell a selection transistor being associated, is described. The process includes growing or depositing a gate dielectric layer for the sensing transistor and for the cell; forming a tunnel mask that extends above the region occupied by the selection transistor for defining the tunnel area; cleaning etching of the gate dielectric layer in the tunnel area up to the surface of the semi-conductor; and growing the tunnel oxide.
The features and the advantages of the process according to the invention will be seen from the description, following herein, of an indicative and not limiting example of embodiment given with reference to the attached drawings.